Access control systems ensure security of a place by restricting access only to authorized personnel. Such systems have become quite important in recent years and have become an essential part of an organization’s security and operations. The important features of an efficient access control system include responding back with accurate identification results in shortest time. Usually, the fingerprints or IR scan is used for pattern matching purposes. An access control system can be developed using any embedded processor however, it is required to provide maximum accuracy within minimum response time. The issue with these systems is that their processing speeds decrease with increase in data size. This research work proposes a solution to this historic issue by designing an access control system with a lower bound for data processing speeds. In 1970s, Reduced Instruction Set Computer (RISC) architecture was introduced to increase the execution speed of processors by simplifying the instruction set architecture (ISA) . With the development of an open-source RISC-V processor in 2010, it has become possible for researchers to optimize the base core making it more efficient according to the required application. To design an optimized RISC-V processor core specifically for access control applications, a detailed research work is carried out. The initial programming code is written in C programming language using compiler offered by Freedom Studio. QEMU emulator is then employed to observe the behavior of registers. SiFive is used as a designing tool for optimizing the base core. The simulation results are to be verified by comparing the code execution times on base core and optimized core.