Analog-to-digital converters (ADC's) are essential components of biomedical devices nowadays. Wireless sensors, wearable devices, and body implanted devices require low-power ADCs. Therefore, achieving higher resolution and bandwidth with lower power consumption is targeted in ADCs design. The Delta-Sigma (∆Σ) modulators are widely used in high precision ADCs, especially for bio-potential signal acquisition, i.e., electroencephalogram (EEG) and electrocardiogram (ECG). The ∆Σ ADCs are required to have a low offset and low flicker noise as the frequency range of these noises overlaps with the signals of interest in EEG and ECG.

In this work, power-efficient ∆Σ ADC for medium-high resolution is proposed. In this work, I will explore a chopper-stabilized high-pass ∆Σ ADC to suppress the offset and low-frequency noises for an EEG signal. The work will target the effective number of bits resolution (ENOB≥12) ∆Σ modulators. The proposed ∆Σ modulator will also incorporate the analog front end for EEG acquisition. The tentative plan is to achieve a total harmonic distortion (THD) of ~-90dB by incorporating current steering digital to analog converters (DAC) and 2-level quantization. The ∆Σ ADC will be simulated, designed, and fabricated using a 180nm CMOS process. The target is to achieve power and an input-referred noise of under 200µW and 5µVrms, respectively, while operating at 1.8V with ENOB of 12 bits.