Event date:
May 20 2022 3:00 pm

Design and Implementation of Real-Time Video Tone-Mapping Algorithm

Dr. Muhammad Adeel Ahmed Pasha
Abdul Rahman Quraishi
EE Reading Room
MS Thesis defense


High Dynamic Range (HDR) displays are used to display HDR images and videos that have more dynamic range than Standard or Low Dynamic Range (SDR or LDR) images and videos. They can depict real world scenes in a fashion which is more natural to human eye. They are still relatively new in the market hence, they will not be able to replace the existing LDR displays in the near future. The contents of HDR images or videos can't be directly displayed on LDR displays because of the incapability of LDR hardware to produce the desired range and contrast of light. For this purpose, tone-mapping is required which maps the large magnitude and range of intensities of HDR image or frame to the 8-bits fixed levels of the LDR image or frame in the range of 0 to 255. Multiple image tone-mapping operators have been proposed that can produce high quality LDR images. However, when they are applied to video sequences, not only the frame rates of the resultant videos are reduced due to slow speed of tone-mapping process, but artifacts such as temporal incoherence and brightness flickering are also introduced. Although their frame rates can be improved by running those tone-mapping algorithms on Graphical Processing Units (GPUs) but GPUs' power consumption makes them non-ideal for embedded and real-time applications. In order to cater for the issues of power consumption and slow processing, Field Programmable Gate Array (FPGA) based hardware-friendly and resource efficient video tone-mapping operator is proposed for low-latency and real-time applications. The proposed video TMO is better than the existing video TMO in software by 20.79x while giving similar tone-mapping quality. Moreover, the hardware implementation of the proposed TMO is 10.78x faster than the MATLAB implementation. Finally, the FPGA implementation of the proposed video TMO is at least 1.99x faster than the existing FPGA implementations of the state-of-the-art video TMOs.

Evaluation Committee 

  • Dr.  Muhammad Adeel Ahmed Pasha (Supervisor)
  • Dr.  Ishtiaq Rasool Khan (Co-supervisor)
  • Dr.  Muhammad Awais Bin Altaf (Evaluator)