Abstract: 
Analog-to-digital converters (ADCs) are essential components of biomedical devices nowadays. Wireless sensors, wearable devices, and body implanted devices require low-power ADCs. Therefore, achieving higher resolution and bandwidth with lower power consumption is targeted in ADCs design. The delta-sigma (ΔΣ) modulators are widely used in high precision ADCs, especially for bio-potential signal acquisition, i.e, Electroencephalogram (EEG) and Electrocardiogram (ECG). The ΔΣ ADCs are required to have a low offset, and low flicker noise as the frequency range of these noises overlaps with the signals of interest in EEG and ECG.

In this work, a power-efficient second-order continuous-time ΔΣ ADC is proposed and implemented. A chopper-stabilized high-pass ΔΣ ADC is designed to suppress the offset and flicker noise while targeting a wearable EEG application. This work targets the effective number of bits resolution (ENOB) of 9.6 bits and achieved a total harmonic distortion (THD) of -107dB. It incorporates current steering digital to analog converters (DAC) and a 2-level quantizer. The ΔΣ ADC is designed. implemented and simulated using the 180nm CMOS process. Power consumption and the input-referred noise of 389 μW and 500nv /√Hz, respectively, are reported, while operating at 1.8V.

Zoom Link:https://lums-edu-pk.zoom.us/j/97677214641?pwd=b25DTDNPZmR4b3cvTXBuUUdwRktlZz09

Meeting ID:    976 7721 4641
Passcode:        047930