Event date:
Feb
22
2021
1:00 pm
Frequency Division Multiplexed Analog Front End for Electroencephalogram Recording Systems
Supervisor
Dr. Muhammad Awais Bin Altaf
Student
Muhammad Shahram Arshad
Venue
Zoom Meetings (Online)
Event
MS Synopsis defense
Abstract
Over the last decade, there is tremendous progress in understanding the working of the brain activities using Electroencephalogram (EEG) signals. EEG signals are being used in detecting disorder such as epilepsy, narcolepsy, trauma, and these signals are also being used in the control of prosthetic devices. These systems are multichannel, bulky, power expensive and require a medical setting for the monitoring of patient's data. There is a need for a wearable EEG acquisition system that could record multiple channels keeping the power and noise requirements of this system low. Analog front end (AFE) contains instrumentational amplifier (IA), and programmable gain (PG) stages, the IA is extremely critical as it is the most power-hungry block to keep the noise requirement low for the acquisition of EEG signals.
The goal of this work is to develop an energy efficient AFE to acquire clean EEG signals. Frequency division multiplexing will be utilized to share the most power-hungry blocks of the AFE while keeping intact the signal to noise ratio. The front-end will be simulated, designed, and fabricated using a 180nm CMOS process. The proposed system will ensure small form factor and low noise while multiplexing at least 2-channels per AFE and solve the 1) 50/60 Hz common-mode interference, 2) in-band noise (mainly 1/f noise and electrode DC offset), and 3) limited input impedance of the IA, in a wearable environment. The target is to achieve power, and an input-referred noise of less than 100µW and 0.7µVrms [0.5-100 Hz], respectively, while operating at 1.8V.
The goal of this work is to develop an energy efficient AFE to acquire clean EEG signals. Frequency division multiplexing will be utilized to share the most power-hungry blocks of the AFE while keeping intact the signal to noise ratio. The front-end will be simulated, designed, and fabricated using a 180nm CMOS process. The proposed system will ensure small form factor and low noise while multiplexing at least 2-channels per AFE and solve the 1) 50/60 Hz common-mode interference, 2) in-band noise (mainly 1/f noise and electrode DC offset), and 3) limited input impedance of the IA, in a wearable environment. The target is to achieve power, and an input-referred noise of less than 100µW and 0.7µVrms [0.5-100 Hz], respectively, while operating at 1.8V.
Zoom Link: https://zoom.us/j/92645222790?pwd=ZG15Mlc2YWFKL05FZ0JBYjdVa0UyUT09
Meeting ID: 926 4522 2790
Passcode: 204994