LUMS faculty continue to distinguish themselves internationally. Dr. Adeel Pasha, Assistant Professor and Director Electronics and Embedded Systems Lab at the Syed Babar Ali School of Science and Engineering (SBASSE), has recently published an article with Mr. Afzal Ahmad, a Research Assistant at SBASSE and LUMS alumnus, in IEEE Transactions on Circuits and Systems II: Express Briefs, a highly prestigious journal.
The article, titled ‘Optimising Hardware Accelerated General Matrix-Matrix Multiplication for CNNs on FPGAs’, deals with Field Programmable Gate Arrays (FPGAs). FPGAs, in contrast to Graphical Processing Units (GPUs), demonstrate massive parallelisation capabilities, at a lower energy cost than GPUs. As a result, FPGAs are being utilised to design Convolutional Neural Networks (ConvNets) accelerators for embedded applications.
In their research, Dr. Pasha and Mr. Ahmad designed an FPGA-based accelerator to improve the efficiency of convolutional layers of an efficient ConvNet architecture. Experimental results showed significant performance improvements against the state-of-the-art FPGA-based implementations of both efficient ConvNets that are tailored towards mobile vision applications, and complex ConvNets that are used in traditional applications.
The full article can be accessed here