Dr. Adeel Pasha Publishes Paper at the International Symposium on Applied Reconfigurable Computing

Tuesday, April 11, 2017

Dr. Adeel Pasha, Assistant Professor and director of the Electronics and Embedded Systems Lab (EESL) at the Department of Electrical Engineering (EE), Syed Babar Ali School of Science and Engineering (SBASSE) published a paper at the International Symposium on Applied Reconfigurable Computing ARC 2017. The article is included in the proceedings published by Springer Lecture Notes in Computer Science (LNCS) as a book chapter, which is indexed by ISI Proceedings and EI-Compendex. The article is resulted from the MS thesis of Dr. Pasha’s student Mr. Muhammad Ali (MSEE-2014). Dr. Umer Farooq (from LiP6, Paris France) Dr. Pasha’a RA Bilal Siddiqui (currently doing PhD @ Purdue University) also contributed in editing the paper.

Background: Reconfigurable computing technologies offer the promise of substantial performance gains over traditional architectures via customising the topology of the underlying architecture to match the specific needs of a given application, even at run-time. Contemporary configurable architectures allow for the definition of architectures with functional and storage units that match in function, bit-width and control structures the specific needs of a given computation. The flexibility enabled by reconfiguration is also seen as a basic technique for overcoming transient failures in emerging device structures. The International Symposium on Applied Reconfigurable Computing (ARC) aims to bring together researchers and practitioners of reconfigurable computing with an emphasis on practical applications of this promising technology.

Title: A Framework for High Level Simulation and Optimisation of Coarse-Grained Reconfigurable Architectures

Abstract: High-level simulation tools are used for optimisation and design space exploration of digital circuits for a target Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuit (ASIC) implementation. Compared to ASICs, FPGAs are slower and less power-efficient, but they are programmable, flexible and offer faster prototyping. One reason for the slow performance in FPGA is their finer granularity as they operate at bit-level. The possible solution is Coarse Grained Reconfigurable Architectures (CGRAs) that work at word-level. There already exists a myriad of CGRAs based on their architectural parameters. However, the CGRA research lacks in design automation since high-level simulation and optimisation tools targeted at CGRAs are nearly non-existent. In this paper, we propose a high-level simulation and optimisation framework for mesh-based homogeneous CGRAs. As expected, the results show that auto-generated homogeneous CGRAs consume 54% more resources when compared with academic FPGAs while providing around 63.3% faster mapping time.

The official abstract can be found here while the complete pre-print is available here.