The main focus of this research cluster is to explore customized hardware, software and
co-design solutions for embedded systems. The development of high speed programmable DSP chips as well as re-configurable and programmable hardware has made it possible that many operations of conventional high performance and low power applications can be implemented in the form of re-usable Silicon IP-cores and associated software code. This not only reduces design time and cost by orders of magnitude but enables manufacturers to maintain a balanced inventory. Important contemporary applications in which these modern system design techniques are being investigated include software defined radios (SDR) and wireless sensor networks (WSN). Other research activity includes hardware based algorithm acceleration in compute intensive systems such as multimedia (image/video) applications. This approach, instead of running the application tasks on a programmable processor, an application specific micro-architecture tailored to the application at hand is generated either by manually written or automatically generated hardware description language (HDL) codes. This approach results in achieving ultra-low-power designs for complex system-on-chip applications.